Senior Staff Engineer – Static Timing Analysis (STA)

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Staff Engineer – Static Timing Analysis (STA) based in India. This is a senior technical leadership opportunity focused on timing analysis and signoff for complex SoC designs and advanced semiconductor technologies.You will lead block-level and full-chip timing closure across multiple operating modes and corners using sophisticated MMMC methodologies.The role involves solving challenging timing issues alongside synthesis, CTS, place-and-route, extraction, and ECO teams.You will also help define timing constraints, drive optimization, and balance performance, power, and area requirements.A strong emphasis is placed on automation and methodology improvements that increase STA productivity and signoff efficiency.You will work within a fast-moving, highly technical environment where ownership, engineering depth, and practical execution are valued.This is an opportunity to contribute directly to advanced AI/HPC silicon infrastructure and help drive successful tapeout of complex designs.